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Altera_Forum
Honored Contributor
Honored ContributorTwo sustom avl mm master to ddr3 uniphy controller
First I have created a custom avl mm master to DDR3 Uniphy controller slave, connected it to DDR3 controller along with pll in QSYS and using that I have perform Write read operations in the DDR3 mem...
Altera_ForumHonored Contributor
Honored Contributorwaitrequest is only valid when an operation is going on, so you shouldn't read it before doing a read or write operation. Did you try to perform a read or write operation anyway?
