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Altera_Forum's avatar
Altera_Forum
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12 years ago

Two sustom avl mm master to ddr3 uniphy controller

First I have created a custom avl mm master to DDR3 Uniphy controller slave, connected it to DDR3 controller along with pll in QSYS and using that I have perform Write read operations in the DDR3 mem...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

This is not how it works. The Avalon specification clearly states that waitrequest is only valid during an operation. Do your read or write operation first, and check waitrequest afterwards. As long as it is 1 then your operation isn't finished and you should wait.

If you do it that way then yes you can have several masters connected to the same slave.