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Vamsi_21's avatar
Vamsi_21
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

TTK failed reading from PHY slave

Hi ,
I have generated a design example using low latency ethernet 10g mac intel Arria 10 fpga ip design example user guide. The link to the design example is below:https://www.intel.com/content/www/us/en/docs/programmable/683063/19-1-19-1/quick-start-guide.html
I have compiled the design by giving appropriate pins and while testing on the hardware, the system console is giving error as below.
error:

TTK failed reading from PHY slave_2000, cannot enable TTK functionality for this PHY. Please verify the reconfig_clk is running and ensure this PHY is not stuck in reset."

I ensured that reconfig_clk is set properly and also tried different jtag clock frequencies(24MHz, 16MHz, 6 MHz).






Ethernet
  • ZiYing_Intel's avatar
    ZiYing_Intel
    2 years ago

    Hi Vamsi,


    I already sent the example design to your email and please check your email.


    Best regards,

    zying


10 Replies

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Vamsi_21,


    Could you try building a simple one channel test design with Native PHY, TX PLL and reset controller and try linking with XCVR toolkit? This would be helpful to narrow down to XCVR channel only.


    Best regards,

    zying


    • Vamsi_21's avatar
      Vamsi_21
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi,
      I have build the design with one XCVR channel only, but it is still showing the same error.

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Vamsi_21,


    Can you try to move away from XCVR toolkit, create signaltap and monitor the TX and RX status to see if they are working fine. Just to isolate any Native PHY issue from XCVR toolkit.


    Best regards,

    zying


    • Vamsi_21's avatar
      Vamsi_21
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi,
      I have tried to view the tx and rx status signals by creating a signaltap file , but the signals are not being captured .
      Below i have put a screenshot of the signaltap window.

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Vamsi_21,

    I just get to know that the EyeQ is no longer supported in A10 devices. It seems to be due to some issue with the EyeQ result. Please avoid using the EyeQ.

    Best regards,

    zying


    • Vamsi_21's avatar
      Vamsi_21
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi,
      Iam not using EyeQ, instead iam using signal tap logic analyzer to monitor the tx and rx status signals.

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Vamsi_21,

    Can you check how many jtag service ports and what index number of desired port by "get_service_paths master" command in the system console?

    This index number is used in the "hwtest/basic/basic.tcl".

    Best regards,

    zying


  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Vamsi,


    I already sent the example design to your email and please check your email.


    Best regards,

    zying


    • Vamsi_21's avatar
      Vamsi_21
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi,
      Thank you for the design.

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Vamsi,


    Thanks for your reply. I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


    Best regards,

    zying