Forum Discussion
Vamsi_21
Occasional Contributor
Occasional ContributorTTK failed reading from PHY slave
Hi , I have generated a design example using low latency ethernet 10g mac intel Arria 10 fpga ip design example user guide. The link to the design example is below:https://www.intel.com/content/www/...
Hi Vamsi,
I already sent the example design to your email and please check your email.
Best regards,
zying
ZiYing_Intel
Frequent Contributor
Frequent ContributorHi Vamsi_21,
Could you try building a simple one channel test design with Native PHY, TX PLL and reset controller and try linking with XCVR toolkit? This would be helpful to narrow down to XCVR channel only.
Best regards,
zying
Vamsi_21Occasional Contributor
Occasional ContributorHi,
I have build the design with one XCVR channel only, but it is still showing the same error.
