Forum Discussion
Vamsi_21
Occasional Contributor
2 years agoTTK failed reading from PHY slave
Hi , I have generated a design example using low latency ethernet 10g mac intel Arria 10 fpga ip design example user guide. The link to the design example is below:https://www.intel.com/content/www/...
- 2 years ago
Hi Vamsi,
I already sent the example design to your email and please check your email.
Best regards,
zying
ZiYing_Intel
Frequent Contributor
2 years agoHi Vamsi_21,
I just get to know that the EyeQ is no longer supported in A10 devices. It seems to be due to some issue with the EyeQ result. Please avoid using the EyeQ.
Best regards,
zying
Vamsi_21
Occasional Contributor
2 years agoHi,
Iam not using EyeQ, instead iam using signal tap logic analyzer to monitor the tx and rx status signals.