TSE, Verilog. MAC/PHY not sending (ARP) packets but PHY's TX led blinks?? SOS!!!

Since I am not that kind of a person who gives up, I was not only waiting for a response but trying different things to make it work and searching for any information I could find. Here is what I did.

Since responding to ARP is a bit more complicated than just sending some packet, I've decided to reduce the complexity and wrote a simple loopback module that does nothing but pipelines incoming data from RX signals and sends that through TX data path (source code can be found here (https://github.com/posedge/sandbox/blob/master/src/net_loopback.v)).

That module is very simple and I believed that it had no errors (which turned out to be true). However, things didn't work for me even with a loopback logic. I did trace signals, all looked good, TX LED blinked but still no luck.

Then I checked MAC settings 10 times, and they looked good. So I moved one level down to the PHY. I've got Arria II GX 6G board that comes with Marvell 88E1111 PHY. TSE MAC works with that PHY through RGMII. Since I've got no specification and knew nothing about configuration registers, I was not sure about how to troubleshoot it. So I went searching through the forum, Google, Russian electronics sites (I am Russian, so I hoped my people could help :-)).

Finally, I ran into the "RGMII with the triple speed ethernet MAC core" post here (http://www.alteraforum.com/forum/showthread.php?t=1010), and this altera's page (http://www.altera.com/support/examples/interfaces-peripherals/exm-tse-rgmii-phy.html). It seems like paul (http://www.alteraforum.com/forum/member.php?u=3147)had a similar problem that he solved by creating a 90 degree shifted clock for the PHY TX signal. I decided to give it a try and did the same - I left one 125 MHz clock connected to the TSE MAC TX signal, added one more clock output into my PLL to produce 125 MHz 90 degrees shifted clock and connected that to the PHY's TX signal. That made the loopback logic work and I was able to see ARP request that I was sending using arping command repeated by the FPGA. Then, I put my logic back and FPGA started sending ARP response confirming that it has IP address in question. All of the code is committed to GitHub, so you can take a look if you are interested.

Here is my arping command working:

$ sudo arping 10.0.0.2 -I eth1
 password for vlad: 
ARPING 10.0.0.2 from 10.0.0.1 eth1
Unicast reply from 10.0.0.2   0.631ms
Unicast reply from 10.0.0.2   0.566ms
Unicast reply from 10.0.0.2   0.614ms
Unicast reply from 10.0.0.2   0.546ms
Unicast reply from 10.0.0.2   0.572ms
Unicast reply from 10.0.0.2   0.606ms

A screenshot of Wireshark showing ethernet packets in question is enclosed.

Huh. I spent the whole weekend on implementing this ARP request/reply thing and it finally works. So I declare myself The Victor and will go get some fresh air and a little bit of alcohol to get ready for a long working week!!!! Woooho!

Did you have timing constraints on your RGMII I/O pins. It was several years ago, but when I tried to make the Cyclone III development kit work with Ethernet (at that time there was no example design with that kit) it didn't work until I put correct timing constraints. I don't think I ever used a shifted clock.

IIRC there is also an MDIO register that you can use to make the 88E1111 shift the RGMII clock itself. But as the datasheet isn't publicly available it's hard to find. I think it was discussed on this forum a while ago too.

Hello,

I am trying to implement a net loopback with Altera TSE MAC.

I found in your reply that you followed a code from github website

https://github.com/posedge/sandbox/blob/master/src/net_loopback.v

but the above link is not working

So can you please post the code for me

It will be a great help

Regards

Arun

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Sirs,

I was slowly "smoking" the TSE user manual, a book on Verilog, some examples... and was writing some silly stuff to wrap my head around all of that. So I have managed to hookup TSE MAC with Marvel PHY (Arria II GX 6G), assign (some) timing constraints, implement double-data buffer to drive RGMII TX CLK and MAC's tx clock, perform a minimal TSE initialization sequence, get and process incoming ethernet packets. All looked good.

So my next step was to actually at least reply to ARP requests (who has IP?). I have hard-coded my MAC address, IP address etc. Wrote the code to send ARP reply, and do a lot of checks meanwhile. Everything looks OK from code perspective, all "debug" checks pass.. PHY's TX LED is blinking. But I get no data on the host - my PC connected directly to the board.

I have tried a lot of things but cannot get it working. I have a feeling that either PHY is sending some crap over the cable and my host (Linux) driver simply drops the signal or I don't know.. I am raging.

Unfortunately (for all of us) I am no good (yet) with debugging things (using Signal Trap etc)...

Here is my code:

network.v (https://github.com/posedge/sandbox/blob/master/src/network.v) - a guy that handles incoming data from TSE and partially parses things.

network_arp.v (https://github.com/posedge/sandbox/blob/master/src/network_arp.v) - a guy that is trying to reply to ARP packets to the point when PHY TX blinks, but no data appears on the other end.

To trace data, I use tcpdump and wireshark. I thought that maybe box is dropping things (eth is in promiscuous mode), but I don't know if there is a way in Linux to trace ethernet signals (probably no?).

Of course, you can also navigate through other sources, from here - https://github.com/posedge/sandbox

(https://github.com/posedge/sandbox)

I must be doing something wrong but I cannot figure out what..

Any hints, help is greatly appreciated.

Thanks!

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