Honored Contributor
Honored ContributorSince I am not that kind of a person who gives up, I was not only waiting for a response but trying different things to make it work and searching for any information I could find. Here is what I did.
Since responding to ARP is a bit more complicated than just sending some packet, I've decided to reduce the complexity and wrote a simple loopback module that does nothing but pipelines incoming data from RX signals and sends that through TX data path (source code can be found here (https://github.com/posedge/sandbox/blob/master/src/net_loopback.v)). That module is very simple and I believed that it had no errors (which turned out to be true). However, things didn't work for me even with a loopback logic. I did trace signals, all looked good, TX LED blinked but still no luck. Then I checked MAC settings 10 times, and they looked good. So I moved one level down to the PHY. I've got Arria II GX 6G board that comes with Marvell 88E1111 PHY. TSE MAC works with that PHY through RGMII. Since I've got no specification and knew nothing about configuration registers, I was not sure about how to troubleshoot it. So I went searching through the forum, Google, Russian electronics sites (I am Russian, so I hoped my people could help :-)). Finally, I ran into the "RGMII with the triple speed ethernet MAC core" post here (http://www.alteraforum.com/forum/showthread.php?t=1010), and this altera's page (http://www.altera.com/support/examples/interfaces-peripherals/exm-tse-rgmii-phy.html). It seems like paul (http://www.alteraforum.com/forum/member.php?u=3147)had a similar problem that he solved by creating a 90 degree shifted clock for the PHY TX signal. I decided to give it a try and did the same - I left one 125 MHz clock connected to the TSE MAC TX signal, added one more clock output into my PLL to produce 125 MHz 90 degrees shifted clock and connected that to the PHY's TX signal. That made the loopback logic work and I was able to see ARP request that I was sending using arping command repeated by the FPGA. Then, I put my logic back and FPGA started sending ARP response confirming that it has IP address in question. All of the code is committed to GitHub, so you can take a look if you are interested. Here is my arping command working:$ sudo arping 10.0.0.2 -I eth1
password for vlad:
ARPING 10.0.0.2 from 10.0.0.1 eth1
Unicast reply from 10.0.0.2 0.631ms
Unicast reply from 10.0.0.2 0.566ms
Unicast reply from 10.0.0.2 0.614ms
Unicast reply from 10.0.0.2 0.546ms
Unicast reply from 10.0.0.2 0.572ms
Unicast reply from 10.0.0.2 0.606ms
