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Altera_Forum's avatar
Altera_Forum
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13 years ago

TSE, Verilog. MAC/PHY not sending (ARP) packets but PHY's TX led blinks?? SOS!!!

Sirs, I was slowly "smoking" the TSE user manual, a book on Verilog, some examples... and was writing some silly stuff to wrap my head around all of that. So I have managed to hookup TSE MAC wi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Did you have timing constraints on your RGMII I/O pins. It was several years ago, but when I tried to make the Cyclone III development kit work with Ethernet (at that time there was no example design with that kit) it didn't work until I put correct timing constraints. I don't think I ever used a shifted clock.

IIRC there is also an MDIO register that you can use to make the 88E1111 shift the RGMII clock itself. But as the datasheet isn't publicly available it's hard to find. I think it was discussed on this forum a while ago too.