Forum Discussion
Honored ContributorTSE 1000BASE-X/SGMII PCS only w/LVDS I/O
Hey Guys,
I know this has been discussed a few times, but I couldn't find the answer I was looking for. I'm using a Stratix IV GX board with the Marvell Phy. I have a stripped down version of a MAC that is working on a Stratix III board using the GMII interface.. We're now trying to use the SGMII interface (ON the IV) with the PCS and PMA (I'm assuming this to be the case when I use the transceiver block with LVDS i/o - please correct me if I'm mistaken). We have a separate MDIO interface and I can read and set the Registers in the PHY (which is AN disabled, Speed 1g, Transmit Enable and SGMII (default). I have the PCS setup as AN disabled, SGMII and Speed 1G (IF_MODE = 0x09) The PCS Control Register is ( full Duplex, 1G) (Control = 0x140) The PCS Status Register is ( Extened Capability, LINK_STATUS, AN ABILITY) (STATUS = 0x09) - not sure why link_status is set - but this doesn't seem to change.. So my problem is nothing seems to pass through the pcs - and I've been floundering for a couple of weeks trying to figure out why.. Any HINTS? Fyi - I inherited all this - so I'm learning as I'm going.. Thanks Much, Elmer.19 Replies
Altera_ForumIf it were me, I would drop in the full MAC implementation with a NIOS and test that your LVDS interface is actually working correctly. Once you've verified the interface works, then you can move on to working with the just the PCS block.
Jake- Altera_Forum
yeah, I've been staring at the reference design that seems to work with the mac/pcs/lvds (it naturally works), but am really curious if anyone has actually got the PCS only to work.. All the PCS status and control registers seem to only reflect info if you have a full blown mac (with mdio) connected to it..
May have to go that route anyway... thanks. - Altera_Forum
I have not used the PCS block in isolation yet but I considered it once. The biggest caveat I observed was that the interface uses a clock enable which becomes active in 10Mbps and 100Mbps mode. However, it sounds like you're running in 1Gbps mode so that would not be an issue.
Jake - Altera_Forum
yeah, if I were to run at the lower speeds I believe I would need to Enable the SGMII bridge.. but I just need the 1 speed (and traffic is actually minimal).
so if you get bored.... thks. - Altera_Forum
hi, i also use this ip,but i used alt2gxb,but i do not know how to config the ff_tx_clk and ff_rx_clk, i used internal fifo withe 8 bit width,if i used 100M mac,ff_tx_clk=25M?or 50M?and ff_rx_clk=100M?
or when i use 1000Mac,should i used ff_rx_clk=1000M? can you tell me?thank you very much - Altera_Forum
what are you using to read/write to the fifo's? ff_x are the read and writes to the FIFO yes? the PCS generates rx and tx clocks not sure if they're related to the various rates.. Something you probably have to play around with..
Elmer. - Altera_Forum
Well, just in case anybody is wondering...
if you're using the Marvell phy and PCS only option of the TSE it does work if you switch over to 1000BASE-X. Key is to have Auto-Negotiation Enabled (PCS), and set the FD bit in the dev_ability register (PCS). Make sure 1000BASE-X in the if_mode (PCS) register is set too. On the Marvell Phy enable the same (GBIC mode with AN enabled). Gave up on SGMII mode. Elmer. - Altera_Forum
How to get the PCS/PMA to work in SGMII mode?
I've done everything but still can't get the MAC with PCS/PMA to work in SGMII mode, external is a Marvell PHY 88E1111. I always get same values for the dev_ability and partner ability register: 0x41a0 which means everything is correct for Base1000-X mode. The funny thing is if i hold the reset of PHY ==> also having same values. haha!!! Control Register of PCS: 0x1140 Status: 0x2d (done negotiation) But if i use reference design from Altera (TSE mac is instantiated in SOPC), without doing anything, just read back those PCS values, I have correct value for Partner Ability register, in SGMII mode which is 0xd801. ... What else can i do? Jeff - Altera_Forum
Well I do know that the MAC comes up in 1000-baseX mode. It has to be placed in SGMII mode by writing to a register within the MAC.
Jake - Altera_Forum
This might seem obvious but it bit me in the rump, Do you have a valid license for the TSE? - Seems the thirty day trial expires as soon as it's not tethered.. Elmer.
