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Altera_Forum's avatar
Altera_Forum
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12 years ago

TSE- Management Interface doesn't capture the input data

Hi to all,

I try to read register data of an external phy device (88E1111, GX-Evalkit). The phy device responce the read access with correct data, but at the output of the input buffer or bidirectional buffer there are no data available. The TSE sets the OE pin to high during send and low during receiving. That's all correct, but I can't see any activity after TSE mdio_oe goes to low. I can measure that at the mdio PU outside of the FPGA are the activities correcly.

Please see also the attachment:

C1: mdio_in (serial data for TSE)

C2: OE of the output buffer

C3: MDC = 2MHz

C4: MDIO outside at PU of the PHY

I tried with different driver strength (4mA, maximum) and change the buffer type with separatly ibuf and obuft, no changes.

Does anyone has an idea?

Best regards

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Did you use HDL to control the MDIO data pin on the FPGA from the mdio_in / mdio_out / mdio_oe signals? If yes can you share it?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    This problem is resolved: the io-buffer pushed to the highest (top) level.

    But I wonder, if I measure at the management interface the first write access for reading data from the external PHY. I execute a write access to the offset 0x84 with REG_AD, MDIO_DEVAD and MDIO_PRTAD. I thoght, that this write access is for configuring the TSE itself. But I measure during MDIO interface a write access to the PHY device with the REG_AD=0x04 and REG_AD=0x11. Why? This could be a critical write access to the PHY register! In this case it is not, because the writing to the REG_AD =0x04, I would need a second write access (Sw_RESET). Do you have an explanation for this issue?