Forum Discussion
Altera_Forum
Honored Contributor
12 years agoThis problem is resolved: the io-buffer pushed to the highest (top) level.
But I wonder, if I measure at the management interface the first write access for reading data from the external PHY. I execute a write access to the offset 0x84 with REG_AD, MDIO_DEVAD and MDIO_PRTAD. I thoght, that this write access is for configuring the TSE itself. But I measure during MDIO interface a write access to the PHY device with the REG_AD=0x04 and REG_AD=0x11. Why? This could be a critical write access to the PHY register! In this case it is not, because the writing to the REG_AD =0x04, I would need a second write access (Sw_RESET). Do you have an explanation for this issue?