Honored ContributorCan anyone say why ?
I have a single EP design using Avalon MM interconnect and across Cyclone IV, Arria V and Stratix V and I want to support Gen3 X1, X4 and X8 on the Stratix V card ... This is a problem to switch to Avalon ST interconnect for one design point .... Any ideas on how to get around this ? Thanks, Bob.
Honored ContributorThe core doesn't support 256 bit thus it's not able to meet gen3x8 speeds. Altera is moving to use the Avalon mm with chaining Dma. Unless you upgrade to the latest Avmm dma core, your going to be stuck with what's there :) sorry
Honored ContributorThanks Trukng, I can upgrade ... how would I do that ?
Also, there is something called the "Merged Design" that hasd PCISIG compliance support and an application for DMA , g3dma_diag.exe ... I need to add a Bar to that design with IMEM attached to test the gen3 x8 outbound poerformance . Any ideas on how I would do that ?Honored ContributorIs there any notion of mixing ST and MM Avalon in the same design ... I have the PCIe Merged design which is a ST Avalon design and it works with Inbound traffic at Gen 3 x 8 and misses the theroretical throughput by only 3%. I now need to demonstrate Outbound performance .. and need to add a BAR with IMEM behind it but that seems to be where I run into problems ... Is it even possible and how do I exit the QSYS component named DUT that works with another component named APP. ?
Thanks, Bob.Honored ContributorHi Bob
To upgrade to Gen3x8 PCIe Avalon-MM with DMA, you need to choose another core called "V-Series Avalon-MM DMA for PCI Express" User Guide is at http://www.altera.com/literature/ug/ug_pcie_avmm_dma.pdf Reference Design Gen3x8 AVMM 256-bit DMA for External DDR3 - Stratix V is available at: http://www.alterawiki.com/wiki/reference_design:_gen3_x8_avmm_256-bit_dma_for_external_ddr3_-_stratix_vHonored ContributorTo upgrade to Gen3x8 PCIe Avalon-MM with DMA, please choose another core called "V-Series Avalon-MM DMA for PCI Express"
User Guide is at http://www.altera.com/literature/ug/ug_pcie_avmm_dma.pdf Reference Design Gen3x8 AVMM 256-bit DMA for External DDR3 - Stratix V may help: http://www.alterawiki.com/wiki/reference_design:_gen3_x8_avmm_256-bit_dma_for_external_ddr3_-_stratix_vHonored ContributorTo upgrade to Gen3x8 PCIe Avalon-MM with DMA, please choose another core called "V-Series Avalon-MM DMA for PCI Express"
User Guide is at http://www.altera.com/literature/ug/ug_pcie_avmm_dma.pdf Reference Design Gen3x8 AVMM 256-bit DMA for External DDR3 - Stratix V may help: http://www.alterawiki.com/wiki/reference_design:_gen3_x8_avmm_256-bit_dma_for_external_ddr3_-_stratix_vHonored ContributorTo upgrade to Gen3x8 PCIe Avalon-MM with DMA, please choose another core called "V-Series Avalon-MM DMA for PCI Express"
User Guide is at http://www.altera.com/literature/ug/ug_pcie_avmm_dma.pdfHonored ContributorHas anyone here been successful using the AVMM PCIe Gen3x8, V-Series Avalon-MM DMA for PCI Express which in practice is an "example design" to be found in Altera_pcie installation directory? And how about the DDR3 support as external memory?
I have compiled it as a TOP (with success) and programmed the final sof to a Stratix V PCIe Gen3x8 based board, but I could not get the thing to work (not even "lspci" could recognize the board at start up). Anyone can help?Honored ContributorI tried the:
an708 hip_sv_gx_x8_g3_avmm_dma256 Pcie DMA reference design using external DDR3 memory. It compiles successfully but in Qsys I am unable to choose the generation of files for SIMULATION Issue in Qsys Generate -> Generate HDL Simulation: simulation: None -> ok simulation: anything else -> Ko Error: pcie_sv_hip_de_hip_status_0: wrong# args: should be "proc_quartus_synth name" while executing "proc_quartus_synth" (procedure "proc_sim_vhdl" line 2) invoked from within "proc_sim_vhdl altpcie_sv_hip_ast_hip_status_bridge" Error: Generation stopped, 14 or more modules remaining Error: ip-generate failed with exit code 1: 2 Errors, 14 Warnings Error: add_fileset_file: No such file /home/papillon-fpga/altera/14.0/ip/altera/altera_pcie/altera_pcie_hip_256_avmm/mentor/altpcie_fifo.v while executing "add_fileset_file mentor/${vf} VERILOG_ENCRYPT PATH "mentor/${vf}" {MENTOR_SPECIFIC}" (procedure "proc_sim_vhdl" line 19) invoked from within "proc_sim_vhdl altpcie_256_hip_avmm_hwtcl" Error: Generation stopped, 7 or more modules remaining Error: ip-generate failed with exit code 1: 2 Errors, 12 WarningsHonored ContributorThe Status Output bridge is an additional compoent in Qsys, this output brige doesn't support simulation, you may need to disable the Status Output bridge in Qsys, then you should be able to generate the simulation files.
