Stratix V PCIe HIP not supporting Avalon MM Gen3 x8 I/F

I tried the:

an708

hip_sv_gx_x8_g3_avmm_dma256

Pcie DMA reference design using external DDR3 memory. It compiles successfully but in Qsys I am unable to choose the generation of files for SIMULATION

Issue in Qsys

Generate -> Generate HDL

Simulation:

simulation: None -> ok

simulation: anything else -> Ko

Error: pcie_sv_hip_de_hip_status_0: wrong# args: should be

"proc_quartus_synth name"

while executing

"proc_quartus_synth"

(procedure "proc_sim_vhdl" line 2)

invoked from within

"proc_sim_vhdl altpcie_sv_hip_ast_hip_status_bridge"

Error: Generation stopped, 14 or more modules remaining

Error: ip-generate failed with exit code 1: 2 Errors, 14 Warnings

Error: add_fileset_file: No such file

/home/papillon-fpga/altera/14.0/ip/altera/altera_pcie/altera_pcie_hip_256_avmm/mentor/altpcie_fifo.v

while executing

"add_fileset_file mentor/${vf} VERILOG_ENCRYPT PATH "mentor/${vf}"

{MENTOR_SPECIFIC}"

(procedure "proc_sim_vhdl" line 19)

invoked from within

"proc_sim_vhdl altpcie_256_hip_avmm_hwtcl"

Error: Generation stopped, 7 or more modules remaining

Error: ip-generate failed with exit code 1: 2 Errors, 12 Warnings