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Altera_Forum
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11 years ago

Stratix V PCIe HIP not supporting Avalon MM Gen3 x8 I/F

Can anyone say why ? I have a single EP design using Avalon MM interconnect and across Cyclone IV, Arria V and Stratix V and I want to support Gen3 X1, X4 and X8 on the Stratix V card ... Th...
Altera_Forum's avatar
Altera_Forum
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11 years ago

The Status Output bridge is an additional compoent in Qsys, this output brige doesn't support simulation, you may need to disable the Status Output bridge in Qsys, then you should be able to generate the simulation files.