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Altera_Forum
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11 years ago

Stratix V PCIe HIP not supporting Avalon MM Gen3 x8 I/F

Can anyone say why ? I have a single EP design using Avalon MM interconnect and across Cyclone IV, Arria V and Stratix V and I want to support Gen3 X1, X4 and X8 on the Stratix V card ... Th...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Is there any notion of mixing ST and MM Avalon in the same design ... I have the PCIe Merged design which is a ST Avalon design and it works with Inbound traffic at Gen 3 x 8 and misses the theroretical throughput by only 3%. I now need to demonstrate Outbound performance .. and need to add a BAR with IMEM behind it but that seems to be where I run into problems ... Is it even possible and how do I exit the QSYS component named DUT that works with another component named APP. ?

Thanks, Bob.