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rsing108's avatar
rsing108
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

STRATIX 10 PCIE + HARD IP ERROR WHILE SIMULATING EXAMPLE DESIGN ON MODELSIM

Hi,

I am trying to simulate the Avalon memory mapped Intel Stratix® 10 Hard IP+ for PCIE example design for Stratix 10 MX by following the instructions of https://www.intel.com/content/www/us/en/programmable/documentation/sox1520633403002.html#xvu1520633284604, but while running "ld_debug" command I am getting errors like

# ** Error: /tools/Intel/quartus_pro/19.3.0.222/quartus/eda/sim_lib/ct1_hssi_atoms.sv(5646): Questa has encountered an unexpected internal error: ../../src/vlog/vgenexpr.c(12502). Please contact Questa support at http://supportnet.mentor.com/
# ** Error: (vopt-2064) Compiler back-end code generation process terminated with code 2.

I tried this using both quartus pro 19.3 and 19.4.

my modelsim version is 10.5c

Also, attaching the full transcript.

7 Replies

  • BoonT_Intel's avatar
    BoonT_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hello Sir,


    I tried to generate the STRATIX 10 PCIE + HARD IP example design and run in modelsim, I can run successfully. Below is the transcript.

    Look on the error on your side, seem like the error is generate from the simulator but not the IP file. You should contact the simulator (mentor) for help.


    ----------------------------------

    # INFO: 137284 ns DMA Write: Got Status

    # original data is 00000000000000020000000400000006

    # write back data is 00000000000000020000000400000006

    # INFO: 137294 ns Passed: 4096 same bytes in BFM mem addr 0x00008000 and 0x00004000

    # Finished comparison!

    # SUCCESS: Simulation stopped due to successful completion!

    # Simulation passed

    # ** Note: $stop : ../../../ip/pcie_ed_tb/DUT_pcie_tb_ip/altera_pcie_s10_tbed_191/sim/altpcietb_g3bfm_log.v(124)

    # Time: 137294610 ps Iteration: 0 Instance: /pcie_ed_tb/dut_pcie_tb/dut_pcie_tb/g_bfm/p_dut_ep/altpcietb_bfm_top_rp/g_bfm/genblk1/rp/inst/apps/g_root_port/genblk1/drvr

    # Break in Function ebfm_log_stop_sim at ../../../ip/pcie_ed_tb/DUT_pcie_tb_ip/altera_pcie_s10_tbed_191/sim/altpcietb_g3bfm_log.v line 124


  • BoonT_Intel's avatar
    BoonT_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hi Sir,

    Here is the version.


    acds/20.2/50,modelsim_se/2020.2



    • rsing108's avatar
      rsing108
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Thanks @BoonT_Intel . I think there is an issue with the modelsim version 16.5c I am using. Will try updating to a newer version and post an update. Thanks for you help.

    • rsing108's avatar
      rsing108
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Updated my modelsim version to 10.6g. The issue is fixed now. Thanks @BoonT_Intel for all your help.