STRATIX 10 PCIE + HARD IP ERROR WHILE SIMULATING EXAMPLE DESIGN ON MODELSIM

Hello Sir,

I tried to generate the STRATIX 10 PCIE + HARD IP example design and run in modelsim, I can run successfully. Below is the transcript.

Look on the error on your side, seem like the error is generate from the simulator but not the IP file. You should contact the simulator (mentor) for help.

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# INFO: 137284 ns DMA Write: Got Status

# original data is 00000000000000020000000400000006

# write back data is 00000000000000020000000400000006

# INFO: 137294 ns Passed: 4096 same bytes in BFM mem addr 0x00008000 and 0x00004000

# Finished comparison!

# SUCCESS: Simulation stopped due to successful completion!

# Simulation passed

# ** Note: $stop : ../../../ip/pcie_ed_tb/DUT_pcie_tb_ip/altera_pcie_s10_tbed_191/sim/altpcietb_g3bfm_log.v(124)

# Time: 137294610 ps Iteration: 0 Instance: /pcie_ed_tb/dut_pcie_tb/dut_pcie_tb/g_bfm/p_dut_ep/altpcietb_bfm_top_rp/g_bfm/genblk1/rp/inst/apps/g_root_port/genblk1/drvr

# Break in Function ebfm_log_stop_sim at ../../../ip/pcie_ed_tb/DUT_pcie_tb_ip/altera_pcie_s10_tbed_191/sim/altpcietb_g3bfm_log.v line 124