Stratix 10 DDR EMIF pin map implements works for example design but fails for our board design

Hi Adzim,

Sorry, I completely missed your earlier response. I was able to resolve the error.

ed_synth is the example design generated by quartus. I modified it to have two instances of EMIF to replicate what we have in our design. ddr_u1 is our internal design with all other interfaces, clocks and internal logic. It has two EMIF instances.

As I had explained, whoever designed the board earlier did a mistake and some I/Os of both EMIF were on a common I/O bank which rendered those IOs unusable and we were limited to access a smaller size of DDR4. When I split the IOs using the common bank, across two banks, the extra I/O bank used also had reference clock coming in. So quartus fit flagged an error. But the error messages were not helpful as the fit errors were in a bank complete EMIF IO. and not in the bank where the reference clock was coming in. I copared that bank with the other banks and the other instance which implemented fine and experimented with moving the reference clock to other bank and it worked.

The tool does need to give more readable/understandable errors for EMIF implementatioon.

Best,

BB