BKB
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Re: Input signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5
Hi Aqid, Thanks for you help. I did not get any concrete solution from FTDI too. I think its the delay of the board. With OE taking its time to travel and data taking its time to travel back so that makes RXF_N to apper valid for a cycle longer. Anyways. you can close this request. Thanks BharatRe: Need help with timing constraints/closure for an EMIF design
Thanks Richard. No, I don't have any specific inquiry except that if you have a script or function that can accept a file and convert all asynchronous to synchronous reset, that would help tremendously. I am having issues with the script I am trying, even with chatgpt. you can transition this tread to community support. Best, BharatRe: Input signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5
Hi, We tried using the logic analyzer and the signal quality degraded. I started seeing the FTDI chip missing clock signals. I agree with your assessment that, mismatch of delays, accumulated over the connector, cable and then board trace would be causing this. When I try to sample the 66MHz FTDI clock and data and control interface, I do see about 2 cycle (5 ns) variation in the data settling to steady value on signaltap. There could be similar variations on the RXF_N signal. I am out of ideas on how to make this work, as to what special consideration I need in the design or if it is just a matter of constraining it. Let me know if you have any suggestions. I am also commuicating with FTDI support. Will update with further development. Best, BharatRe: Need help with timing constraints/closure for an EMIF design
Hi Richard, Below are some messages I see in the fit report. ; Retiming Restrictions at Register #1: ; ; u_fpga_mem_subsystem_2|fpga_mem_subsystem_1_MC_0|mc|mc_half_0|mc_ior_row|memory_controller_row|u_rs8_decode|gen_p3_pipe.handshaking_phase3|TX_data[46] ; ; Node uses an asynchronous clear port ; Retiming Restrictions at Register #1: ; ; u_fpga_mem_subsystem_2|fpga_mem_subsystem_1_MC_1|mc|mc_half_0|mc_ior_row|memory_controller_row|u_rs8_decode|u_rs8_berl_l|handshaking_phaseA|TX_data[6]~RTM_41 ; ; Node uses an asynchronous clear port ; ; ; ; Retiming Restrictions at Register #2: ; ; u_fpga_mem_subsystem_2|fpga_mem_subsystem_1_MC_1|mc|mc_half_0|mc_ior_row|memory_controller_row|u_rs8_decode|u_rs8_berl_l|handshaking_phase1|TX_data[53]~RTM_541 ; ; Node uses an asynchronous clear port ; Below is a message from fit.fastforward.rpt ; Retiming Restrictions at Register #16: ; ; u_fpga_mem_subsystem_2|fpga_mem_subsystem_1_MC_1|mc|mc_half_0|mc_ior_row|memory_controller_row|gen_rs8_pipe2.handshaking_pipeline_dec|TX_data[100]~RTM ; ; Node uses an asynchronous clear port Those also form the path where I think the timing failures are. I did see many more messages earlier stating "cannot force asynchronous clear....". don't exactly remember the complete message. But with this build also I see timing failures for about 2.5 on 200MHz clock. Best, BharatHow to determine if FPGA is faulty/stopped working
Hi, Die U2 in one of the dual die FPGA (1SG10MHN3F74C2LG) in one of our board is stopped working. Die U1 works but Die U2 does not. The same design in other FPGA die U2 works. I understand that It can be done by looking at the config_done signal, but I guess that would require to probe the pin. Please let me know if there is any other way to determine if one of the die is not working. Also please let me know any other thoughts on why the 2nd die of one of the FPGA is not working and what should I be looking at to confirm. Please let me know if I can provide any other information. Best, BBRe: Input signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5
Hi As suggested here earlier, I changed FTDI interface within the FPGA to operate on the negative edge of FTDI clock. I still see the same issues i.e. RXF_N is asserted (low) and the data on the data bus is not valid data. The FTDI interface along with its clock is sampled with 400 mhz clock. Best BharatRe: Need help with timing constraints/closure for an EMIF design
HI Richard I haven't yet converted the asynchronous reset to synchronous. I will get to it tomorrow. I can share the archive of the design. Please let me know if I should upload it somewhere else or send to a any specific email address. Best, Bharat
