Strange problem with DCFIFO

Hi,

in my design, I'm using two dual clock FIFOs for buffering. While one is running without any problem, the other one is doing something strange when loading the design to the FPGA (DE1-SoC).

Some details: The FIFO has a writing clock of 25MHz and a reading clock of 143MHz, overflow / underflow protection are enabled and it has a size of 16bit x 512 words. I'm using the rdusedw (named as FIFO_READUSED) port

to generate my own request signal (c_mem_xxx are integer constants)

 signal s_read_used   : integer range 0 to 511;
 signal s_data_request : std_logic_vector (1 downto 0);
....
(some lines removed)
...
 --generate DATA_REQUEST signal
 s_read_used <= to_integer(unsigned(FIFO_READUSED));                            <===(1)
 --s_read_used <= 260;                                                          <===(2)
 s_data_request <= "11" when (s_read_used > c_mem_high) else
       "10" when (s_read_used >= c_mem_half) else
       "01" when (s_read_used > c_mem_low) else "00";
....

The strange thing is, that the simulation runs as expected but when loading the design on the FPGA is behaves strange. I've connected some of the rdusedw signals to the LEDRs on the board as well as my data request signal

to observe them. Now when I'm using line (2), everything is fine. But when I'm using line (1) the FIFO seems to get stuck (the rdusedw signal is stuck at 0 and so does my data_request signal). I really have no idea about the

reasons...

My second FIFO is implemented in exactly the same way with the difference that I'm using the wrusedw signal - and this FIFO is running as expected.

So, does someone have any idea about what's going on here?

I've tried a lot of different things (e.g. removing the integer things and using only unsigned, ...) without finding a solution.

Best,

Martin