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Altera_Forum
Honored Contributor
Honored ContributorStrange problem with DCFIFO
Hi, in my design, I'm using two dual clock FIFOs for buffering. While one is running without any problem, the other one is doing something strange when loading the design to the FPGA (DE1-SoC). ...
Altera_ForumHonored Contributor
Honored ContributorWhy not post the code/project that exhibits the problem?
