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Altera_Forum's avatar
Altera_Forum
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8 years ago

Strange problem with DCFIFO

Hi, in my design, I'm using two dual clock FIFOs for buffering. While one is running without any problem, the other one is doing something strange when loading the design to the FPGA (DE1-SoC). ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Thanks for your reply.

Yes, I don't have any warning generated by TimeQuest when using the PLL reset sources. When using my reset logic, I get 4 warnings (probably because I haven't added constraints in the sdc file yet).

However, I observe the mentioned behavioral in both cases.