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Altera_Forum's avatar
Altera_Forum
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8 years ago

Strange problem with DCFIFO

Hi, in my design, I'm using two dual clock FIFOs for buffering. While one is running without any problem, the other one is doing something strange when loading the design to the FPGA (DE1-SoC). ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Ok, I did some further investigations but still I have no idea why this is happening.

I don't think that the problem is timing related since I get no message from Time Quest around this part of the design.

Like written above, I use some of the LEDs of the DE1-SoC board to display the current value of rdusedw.

When I use this signal in any possible way (like simply forwarding two of the bits), all LEDs stay dark indicating the FIFO to be always empty. But when I remove every line of VHDL code containing the rdusedw signal, the

LEDs show the current value of elements stored in the FIFO as expected.

So is there something is miss or do I have to add special Contraints to the SDC file to see if something is wrong with the timing?

PS: I took a closer look on the RTL schematic and there is nothing between the output register of the FIFO and the input register of my design (when reading the rdusedw inside my clocked process @143MHz)