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treble99's avatar
treble99
Icon for New Contributor rankNew Contributor
2 years ago

Simulating PCIE_DDR4: what are the complete setup contents.

Hello,

I am trying to simulate the reference PCIE_DDR for the Terasic De5a-NET DDR4 board. I was referring to Intel Documentation https://www.intel.com/content/www/us/en/docs/programmable/683162/23-1-2-7-0/simulating-external-memory-interface.html

My questions are:

1. Is following section 2.6 sufficient in running simulation? [Attached Screenshot]

The msim_setup.tcl script is just sourcing device and design libraries etc. At what parts is it driving the design?

I can run ld_debug and I do see Objects in window. But I want to meaningfully verify DDR read/writes in simulation.

2. If a separate testbench script is needed which in turn sources msim_setup.tcl. Where can I find an example of such a testbench?

The `Generate` -> `Generate Testbench System` option in my understanding stops at providing msim_setup.tcl script.

Further this design used PCIe Hard IP. BFM are one such way of simulation.

3. Is there a BFM testbench script available for reference?

I was not able to find it. And it is confusing to build one owing to complex design(atleast for me.)


An answer to above questions is greatly appreciated.
I can also provide additional information if needed.

Thank you,
Manish

Memory
Pcie

6 Replies

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    1. Is following section 2.6 sufficient in running simulation? [Attached Screenshot]

    >> Are you trying to simulate PCIe design or Emif design ?

    >> if it is memery interface issue, you may refer to our official youtube channel which there got step by step guide to run the simulation

    >> https://www.youtube.com/watch?v=iCr-0eOwo9o&ab_channel=IntelFPGA


    2. If a separate testbench script is needed which in turn sources msim_setup.tcl. Where can I find an example of such a testbench?

    >> Please refer to answer in question 1, the video shall explain how you generate the testbench for simulation


    3. Is there a BFM testbench script available for reference?

    Can I know which tile that you are referring for the PCIe HIP ? P-tile ? R-tile or others...


    Regards,

    Wincent_Intel


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,

    I wish to follow up with you about this case.

    Do you have any further questions on this matter ?

    ​​​​​​​Else I would like to have your permission to close this forum ticket

    Regards,

    Wincent_Intel


  • treble99's avatar
    treble99
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hello Wincent,


    Please refer to answer in question 1, the video shall explain how you generate the testbench for simulation

    Thank you for the link I am reviewing it and I will get back to you by the end of this week. Primarily I am not still not sure where the stimulus is sent from, driving the signals.


    Are you trying to simulate PCIe design or Emif design ?

    In the PCIe_DDR example I want to simulate reading/writing to DDR memory. I want to verify meaningfully some data being read and written to DDR. Please suggest the setup for it.


    Can I know which tile that you are referring for the PCIe HIP ? P-tile ? R-tile or others...

    I have not worked on PCIe designs before, can you please point out where I can find this information for you.

    Thank you,

    Manish

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    Please refer to answer in question 1, the video shall explain how you generate the testbench for simulation

    Thank you for the link I am reviewing it and I will get back to you by the end of this week. Primarily I am not still not sure where the stimulus is sent from, driving the signals.

    >> the video shall be clear, please refer and try to run it.



    Are you trying to simulate PCIe design or Emif design ?

    In the PCIe_DDR example I want to simulate reading/writing to DDR memory. I want to verify meaningfully some data being read and written to DDR. Please suggest the setup for it.

    >> for PCIe_DDR you may refer to https://www.intel.com/content/www/us/en/docs/programmable/683390/quartus-prime-pro-v17-0-arria-10/pci-express-dma-reference-design-using.html


    Can I know which tile that you are referring for the PCIe HIP ? P-tile ? R-tile or others...

    I have not worked on PCIe designs before, can you please point out where I can find this information for you.

    Is okay, you are using Arria 10, it is PCIE Hard IP.


    Regards,

    Wei Chuan


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,

    I wish to follow up with you about this IPS case.

    Do you have any further questions on this matter ?

    ​​​​​​​Else I would like to have your permission to close this IPS ticket

    Regards,

    Wei Chuan


  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi

    We have not hear from you and this Case is idling. It is not recommended to idle for too long.

    Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

    Hence, This thread will be transitioned to community support.

    If you have a new question, feel free to open a new thread to get support from Intel experts.

    Otherwise, the community users will continue to help you on this thread. Thank you

    If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me of the cause so that I can learn from it and strive to enhance the quality of future service experiences.

    Regards,

    Wincent_Intel