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treble99's avatar
treble99
Icon for New Contributor rankNew Contributor
2 years ago

Simulating PCIE_DDR4: what are the complete setup contents.

Hello, I am trying to simulate the reference PCIE_DDR for the Terasic De5a-NET DDR4 board. I was referring to Intel Documentation https://www.intel.com/content/www/us/en/docs/programmable/683162/23-...
Memory
Pcie
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


1. Is following section 2.6 sufficient in running simulation? [Attached Screenshot]

>> Are you trying to simulate PCIe design or Emif design ?

>> if it is memery interface issue, you may refer to our official youtube channel which there got step by step guide to run the simulation

>> https://www.youtube.com/watch?v=iCr-0eOwo9o&ab_channel=IntelFPGA


2. If a separate testbench script is needed which in turn sources msim_setup.tcl. Where can I find an example of such a testbench?

>> Please refer to answer in question 1, the video shall explain how you generate the testbench for simulation


3. Is there a BFM testbench script available for reference?

Can I know which tile that you are referring for the PCIe HIP ? P-tile ? R-tile or others...


Regards,

Wincent_Intel