Simulating PCIE_DDR4: what are the complete setup contents.

Hello Wincent,

Please refer to answer in question 1, the video shall explain how you generate the testbench for simulation

Thank you for the link I am reviewing it and I will get back to you by the end of this week. Primarily I am not still not sure where the stimulus is sent from, driving the signals.


Are you trying to simulate PCIe design or Emif design ?

In the PCIe_DDR example I want to simulate reading/writing to DDR memory. I want to verify meaningfully some data being read and written to DDR. Please suggest the setup for it.


Can I know which tile that you are referring for the PCIe HIP ? P-tile ? R-tile or others...

I have not worked on PCIe designs before, can you please point out where I can find this information for you.

Thank you,

Manish