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Altera_Forum's avatar
Altera_Forum
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18 years ago

Should I expect critical warnings in DDR IP code?

I have a 7.2 design with the Altera DDR SDRAM controller megacore function.

My design seems to work but I am getting the following critical warnings:

Critical Warning: (Critical) Rule A102: Register output should not drive its own control signal directly or through combinational logic. Found 1 combinational loops related to this rule.

Critical Warning: (High) Rule A103: Design should not contain delay chains. Found 3 delay chains.

Critical Warning: (High) Rule R101: Combinational logic used as a reset signal should be synchronized. Found 2 node(s) related to this rule.

When I try and locate the error in the design file I get a pop-up saying "Cannot open encrypted file .../pzdyqx.vhd -- license file support for this file includes compilation support, but does not include viewing support"

Should I ignore these?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    First, Which DDR controller are you using? Is it the High Performance controller?

    Do you have a license for this DDR SDRAM controller? Are you using any other Altera IP? Do you have a license for all of the IP in the design?

    If you don't have a license for every IP core in your design, then I believe that these messages may be coming from the OpenCore Plus H/W evaluation logic. In this case, these messages can be safely ignored. See AN320 on the Altera website which describes these warnings.

    If you have a license for all of the IP in your design, then you probably should not be getting these warnings, and the warnings may be pointing to a real problem.

    If you post the full text of the warning messages by expanding them, I might be able to tell you more.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Excellent answer! I am using OpenCore, as my subscription expired during 7.1, and when I tried to invoke the grace period, I found it doesn't include IP support, so I dropped back to the web version of 7.2!

    This also seems to answer another question I had. Where is sld_hub coming from? No doubt it disappears when I get rid of the OpenCore ... To bad Altera couldn't have put some hardware support like a global reset tied to to the JTAG block for OpenCores support. That might make OpenCores more transparent. I wonder if the cost per chip would have been significant ...

    Anyway, as I said, a great answer. Looks like you "hit the nail on the head".

    Thanks

    Steve
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Have a look at AN320. It explains most of what I said. The SLD_HUB does come from OpenCore Plus. I am glad that I hit the nail on the head. It was an educated guess.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I have Problem with Rule R101. I'm using web edition. I've tried to put some registers between processor and Reset signal input, but with no effect. How to synchronize that reset signal? In addition I have 3 more crit. warnings "Timing requirements not met". I think, that they aren't so important because I have made these settings:

    create_clock -name Clock -period 20 [get_ports clk_0]

    derive_clock_uncertainty

    in my .sdc file.

    So can u help my with that problem?

    I really appreciate.