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Altera_Forum's avatar
Altera_Forum
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18 years ago

Should I expect critical warnings in DDR IP code?

I have a 7.2 design with the Altera DDR SDRAM controller megacore function. My design seems to work but I am getting the following critical warnings: Critical Warning: (Critical) Rule A102: Regi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I have Problem with Rule R101. I'm using web edition. I've tried to put some registers between processor and Reset signal input, but with no effect. How to synchronize that reset signal? In addition I have 3 more crit. warnings "Timing requirements not met". I think, that they aren't so important because I have made these settings:

create_clock -name Clock -period 20 [get_ports clk_0]

derive_clock_uncertainty

in my .sdc file.

So can u help my with that problem?

I really appreciate.