Serialite II data rate on Stratix - 4 FPGA

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STRATIX-4 FPGA which has transceivers supporting up to 8.5Gbps per lane

I am planning to use Serialite II protocol but when i read the specification of Serilatite it shows only upto 6.375 Gbps

I am providing the link below

http://www.altera.com/products/ip/iup/seriallite/m-alt-seriallite2.html

Can i know why even the transceiver supporting 8.5 Gbps why Serialite specifying only 6.375 Gbps

Please suggest is this 6.375 Gbps is the raw data rate or link data rate

Please help me as we need to choose a FPGA based on the data rate of transceiver

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The Stratix IV transceivers can only operate at above 6.5Gbps by disabling the majority of the features in the PCS block (part of the hard IP block). On the link you sent is the comment:

"Link reliability is enhanced by the 8B/10B encoding scheme"

and this is one of the features of the hard ip that is disabled above 6.5Gbps.

You can still implement 8/10B encoding, its just that you have to do everything in the fabric.

What are you trying to implement?

Cheers,

Dave

Hi

Thank you very much for you kind and prompt reply

One of my friend told that Serialite II supports only 6.375 Gbps

Out of which if we remove 25% for all redundancy(8b/10 clock correction,alignment etc) than the RAW data rate supported by Serialite-II protocol is 4.78125 Gbps

I am wandering if the link supports 8.5 Gbps than removing 25% redundancy we should reach up to 6.375 Gbps data rate

I would like to know weather the above suggestion that serialite imposes a restriction even though the link supports better speed is correct or not

if not I am looking for a protocol which maximum utilizes (8.5Gbps) link speed

Regarding your question

What are you trying to implement?

I need to transfer 128 Gbps(RAW) data between two FPGA's

Regards

M Kalyan srinivas

Dear all

In the STRATIX-4 FPGA there are 16 Transceivers which has PMA alone

without the dedicated PCS sub layer ,I am feared to make use of these

transceivers as there is no PCS Sublayer

I would like to know is there any Soft IP Core available for PCS Sublayer to

make use of these 16 Transceivers.

Regards

M Kalyansrinivas

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I would like to know weather the above suggestion that serialite imposes a restriction even though the link supports better speed is correct or not

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Yes, any scheme that uses 8/10B encoding reduces the link bandwidth. However, that 'loss' comes at the 'gain' of link reliability.

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I am looking for a protocol which maximum utilizes (8.5Gbps) link speed

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You can create your own protocol.

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I need to transfer 128 Gbps(RAW) data between two FPGA's

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128Gbps / 8.5Gbps = 15.05 transceiver lanes.

Read this, see p10

http://www.ovro.caltech.edu/~dwh/wbsddc/high_speed_samplers_notes.pdf (http://www.ovro.caltech.edu/%7edwh/wbsddc/high_speed_samplers_notes.pdf)

The EP4SGX530NF45C2 has 4 transceiver banks down the left and right side of the device.

You could use the 8.5Gbps lanes in 4 of the transceiver banks for a maximum speed of 4 x 4 x 8.5 = 136Gbps.

You could write your own 64/66B encoding scheme in the fabric, and get an effective data rate of 131.8Gbps. I believe Interlaken uses this encoding, so you could look at using an Interlaken core.

If you are using the links as direct FPGA-to-FPGA links on the same PCB, then you could either DC couple or AC couple. In either case, you need to ensure the link has enough data transitions for the lock-to-data (LTD) mode of the CDR PLLs to work. A pseudo-random binary sequence (PRBS7) sequence can be used for this.

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/lfsr_tutorial.pdf)

The link is initialized by first sending only the PRBS7 pattern between FPGAs, so that the receive-side can be synchronized to the PRBS7 pattern. Once the link is synchronized, you can send data. The data gets XOR'ed with the PRBS pattern at the transmitter, and then XOR'ed again with receive-side PRBS at the receiver. The result is that your data is modulated over the transceiver links, maintaining sufficient bit toggling that an AC coupled link can be used, and the CDR PLLs remain locked when using LTD mode. In this scheme, there is no loss of link bandwidth.

Cheers,

Dave