Serialite II data rate on Stratix - 4 FPGA

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STRATIX-4 FPGA which has transceivers supporting up to 8.5Gbps per lane

I am planning to use Serialite II protocol but when i read the specification of Serilatite it shows only upto 6.375 Gbps

I am providing the link below

http://www.altera.com/products/ip/iup/seriallite/m-alt-seriallite2.html

Can i know why even the transceiver supporting 8.5 Gbps why Serialite specifying only 6.375 Gbps

Please suggest is this 6.375 Gbps is the raw data rate or link data rate

Please help me as we need to choose a FPGA based on the data rate of transceiver

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The Stratix IV transceivers can only operate at above 6.5Gbps by disabling the majority of the features in the PCS block (part of the hard IP block). On the link you sent is the comment:

"Link reliability is enhanced by the 8B/10B encoding scheme"

and this is one of the features of the hard ip that is disabled above 6.5Gbps.

You can still implement 8/10B encoding, its just that you have to do everything in the fabric.

What are you trying to implement?

Cheers,

Dave