Serialite II data rate on Stratix - 4 FPGA

Hi

Thank you very much for you kind and prompt reply

One of my friend told that Serialite II supports only 6.375 Gbps

Out of which if we remove 25% for all redundancy(8b/10 clock correction,alignment etc) than the RAW data rate supported by Serialite-II protocol is 4.78125 Gbps

I am wandering if the link supports 8.5 Gbps than removing 25% redundancy we should reach up to 6.375 Gbps data rate

I would like to know weather the above suggestion that serialite imposes a restriction even though the link supports better speed is correct or not

if not I am looking for a protocol which maximum utilizes (8.5Gbps) link speed

Regarding your question

What are you trying to implement?

I need to transfer 128 Gbps(RAW) data between two FPGA's

Regards

M Kalyan srinivas