New ContributorSERDES IP not compiling after migrating to Quartus Pro 23.1
Hello,
I am using LVDS SERDES IP on Arria 10 for RX DPA-FIFO which works on Quartus Prime17.1. The input data are all located on bank 3 and the reference clock comes from the output of an IOPLL.
After migrating to Quartus Pro 23.1 it doesn’t compile anymore.
Error(18694): The reference clock on PLL"adc_if|lvds_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll",which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.
Error: Failed to synthesize partition
It seems like the pin locations of data and clock are more restrictive in the newer version. It only compiles if the location of data pins are all in the same I/O bank and the clock comes from a dedicated clock pin from that same bank. It also fails if those pins are in the same bank number but different bank letter (e.g. 3D and 3F)
Error(14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 LVDS_CHANNEL(s)). Fix the errors described in the submessages, and then rerun the Fitter.
Is there a workaround to for this? Either to make it work within pins from the same bank number (different letter) or from the output of an IOPLL like in previous versions.
Thanks in advance
