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RVanD5's avatar
RVanD5
Icon for New Contributor rankNew Contributor
3 years ago

SERDES IP not compiling after migrating to Quartus Pro 23.1

Hello, I am using LVDS SERDES IP on Arria 10 for RX DPA-FIFO which works on Quartus Prime17.1. The input data are all located on bank 3 and the reference clock comes from the output of an IOPLL. ...
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
3 years ago

Hello,
Error(14566) can be probably fixed by adding a Global Clock assignment to the dedicated clock pin. Error(18694) has been introduced in QPP 18.1, up to 18.0, SERDES refclock could be routed through core. You'll find all related forum discussion and support notes by searching for the error number.

As error message and forum statements suggest, Intel has blocked SERDES refclock routing in QPP to save the max data rate specification. I feel they threw the baby out with the bath water. Everybody knows that clock routing involves additional jitter, nevertheless it could be and has been widely used with Intel FPGA.

A possible solution could be that an option to enable refclock routing is disclosed to the public, to be used at your own risk. I bet that the option already exists, a cautious programmer won't cut existing functionality without creating a legacy option.