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RVanD5
New Contributor
New ContributorSERDES IP not compiling after migrating to Quartus Pro 23.1
Hello,
I am using LVDS SERDES IP on Arria 10 for RX DPA-FIFO which works on Quartus Prime17.1. The input data are all located on bank 3 and the reference clock comes from the output of an IOPLL. ...
AqidAyman_Altera
Regular Contributor
Regular ContributorHi,
I guess it is not possible to make the LVDS RX work among adjacent banks as per the latest Handbook has mentioned this.
"For differential receivers, the PLL can drive only the channels within the same I/O bank."
You can refer to the link for more information:
Regards,
Aqid
