SDRAM Controller

I know that: Burst length use for determining the number of clock.But i dont know that: if i chose burst length 1 or burst length 2, burst length 4, burst length 8, how many clock in each case?

any body can help me?

reg  Memory ;

parameter Num_Meg    =  8; //  8 Mb
parameter Data_Width =  4; //  4 bits
parameter Num_Bank   =  4; //  4 banks
parameter MEG = 21'h100000;

Yes, there seems to be a Quartus limitation. Actually simulating large memory sizes slows down simulation considerably, also with ModelSim, although larger memory can be simulated. Thus it's avoided if possible. For verifications of a memory controller design, it's ususally sufficient to simulate a small memory window. Most memory vendor models are utilizing this option.

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
	Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
	Info: Processing started: Wed May 28 23:58:28 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sdr_ctrl -c sdr_ctrl
Info: Found 2 design units, including 2 entities, in source file sdr_ctrl_tb.v
	Info: Found entity 1: sdr_ctrl
	Info: Found entity 2: test_sdr_ctrl
Error (10228): Verilog HDL error at sdr_ctrl.v(4): module "sdr_ctrl" cannot have duplicate definition
Error: Entity "sdr_ctrl" in file sdr_ctrl_tb.v already exists in file sdr_ctrl.v
Info: Found 1 design units, including 1 entities, in source file sdr_ctrl.v
Info: Found 2 design units, including 2 entities, in source file sdr_sig_tb.v
	Info: Found entity 1: sdr_sig
	Info: Found entity 2: test_sdr_sig
Error (10228): Verilog HDL error at sdr_sig.v(8): module "sdr_sig" cannot have duplicate definition
Error: Entity "sdr_sig" in file sdr_sig_tb.v already exists in file sdr_sig.v
Info: Found 1 design units, including 1 entities, in source file sdr_sig.v
Info: Found 2 design units, including 2 entities, in source file sdr_data_tb.v
	Info: Found entity 1: sdr_data
	Info: Found entity 2: test_sdr_data
Error (10228): Verilog HDL error at sdr_data.v(6): module "sdr_data" cannot have duplicate definition
Error: Entity "sdr_data" in file sdr_data_tb.v already exists in file sdr_data.v
Info: Found 1 design units, including 1 entities, in source file sdr_data.v
Error: Quartus II Analysis & Synthesis was unsuccessful. 6 errors, 0 warnings
	Error: Processing ended: Wed May 28 23:58:28 2008
	Error: Elapsed time: 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 6 errors, 0 warnings

 //**********************************************************************
 //                            MODULE CHINH CONTROL INTERFACE
 //**********************************************************************
module sdr_ctrl(
    sys_CLK,  // clock he thong
    sys_RESET,//reset he thong
    sys_R_Wn,//read/write. High: chu ki doc  Low: chu ki ghi
    sys_ADSn,//sdram strobe
    sys_DLY_100US,//tin hieu on dinh trong 100us
    sys_REF_REQ,//tin hieu yeu cau refresh
    sys_REF_ACK,//tin hieu ack tra ve 
    sys_CYC_END,//read/write da xong
    sys_INIT_DONE,//tin hieu khoi tao
    iState,// bien trang thai INIT_FSM
    cState,// bien trang thai CMD_FSM
    clkCNT); //phu thuoc vao burst lenght, cho biet so xung clock
    
.
.
.
.
    input        sys_CLK;
    input        sys_RESET;
    input        sys_R_Wn;
    input        sys_ADSn;
    input        sys_DLY_100US;
    input        sys_REF_REQ;//Tin hieu ngo vao
//*************************************
//            OUTPUT
//*************************************
    output       sys_REF_ACK;
    output       sys_CYC_END;
    output       sys_INIT_DONE;
    output  iState;
    output  cState;
    output  clkCNT;//Tin hieu ngo ra
    reg          sys_INIT_DONE;  // indicates sdr initialization is done
    reg     iState;         // bien trang thai INIT_FSM
    reg     cState;         // bien trang thai CMD_FSM
    reg          sys_REF_ACK;    //tra ve ACK
    reg          sys_CYC_END;    // read/write hoan thanh 
    reg     clkCNT;         //so xung clock 
    reg          syncResetClkCNT; // reset ve 0
.
.
.
endmodule

`include "sdr_ctrl.v"
module test_sdr_ctrl();
reg         sys_CLK;
reg         sys_RESET;
reg         sys_R_Wn;
reg         sys_ADSn;
reg         sys_DLY_100US;
reg         sys_REF_REQ;
wire       sys_REF_ACK;
wire       sys_CYC_END;
wire       sys_INIT_DONE;
wire  iState;
wire  cState;
wire  clkCNT;
sdr_ctrl sdr_ctrl_01(
	    .sys_CLK(sys_CLK),  // clock he thong
	    .sys_RESET(sys_RESET),//reset he thong
	    .sys_R_Wn(sys_R_Wn),//read/write. High: chu ki doc  Low: chu ki ghi
	    .sys_ADSn(sys_ADSn),//sdram strobe
	    .sys_DLY_100US(sys_DLY_100US),//tin hieu on dinh trong 100us
	    .sys_REF_REQ(sys_REF_REQ),//tin hieu yeu cau refresh
	    .sys_REF_ACK(sys_REF_ACK),//tin hieu ack tra ve 
	    .sys_CYC_END(sys_CYC_END),//read/write da xong
	    .sys_INIT_DONE(sys_INIT_DONE),//tin hieu khoi tao
	    .iState(iState),// bien trang thai INIT_FSM
	    .cState(cState),// bien trang thai CMD_FSM
	    .clkCNT(clkCNT)//phu thuoc vao burst lenght, cho biet so xung clock
		); 
		
always begin
	sys_CLK = 1'b0;
# 10 sys_CLK = 1'b1;
# 10;
	   end
initial begin
	sys_RESET = 1'b0;
	sys_R_Wn = 1'b1;
	sys_ADSn = 1'b1;
# 15 sys_DLY_100US = 1'b1;
# 15 sys_REF_REQ = 1'b0;
# 400 sys_REF_REQ = 1'b1;
# 500 sys_R_Wn = 1'b0;
	
# 1000 $finish;
	     end
endmodule

please help me to solve these problems.Thanks in advance

Obviuosly the problem isn't related to SDRAM in particular.

can you explain clearly? How can i fix it?Can you fix it?

Delete this line

`include "sdr_ctrl.v"

As one point: DM ist set to all zero, this means don't write anything. Generally, I can't decide, if the stimulation timing is correct. There is a testbench supplied with the reference design, I would use it as basic test.