SDRAM Controller

any body can help me?

When i compile my testbench, i met bug.But i can not fix it.

reg  Memory ;

Error (10205): Verilog HDL error at sdr_tb.v(135): memory size reaches 2**24 bits limit

p/s:

parameter Num_Meg    =  8; //  8 Mb
parameter Data_Width =  4; //  4 bits
parameter Num_Bank   =  4; //  4 banks
parameter MEG = 21'h100000;

This is my test bench: