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Altera_Forum
Honored Contributor
18 years agoSDRAM Controller
Now, i am researching about SDRAM Controller Core.So o need some document its.Can you help me? Many thanks
Altera_Forum
Honored Contributor
17 years ago --- Quote Start --- As one point: DM ist set to all zero, this means don't write anything. Generally, I can't decide, if the stimulation timing is correct. There is a testbench supplied with the reference design, I would use it as basic test. --- Quote End --- very much! I attached reference design . Please! discuss..... Thank you.