SDRAM Controller

Obviuosly the problem isn't related to SDRAM in particular.

I guess, the problem is in including the design file to test-bench and to the project file list also. Generally, the Verilog include statement is intended for referencing e. g. configuration files. Design files with a name identical to module would be opened automatically by Quartus, if it's also in the project file list, it is scanned twice without previous check.