SDRAM controller: Altera High Performance vs. Microtronix Multi-Port

Hi,

I am also using the 3c120 board for a video processing application and I am facing the same bandwidth issues.

I have split the DDR2 in two separate 32-bit memories. Nios has full access to one while the other is shared by the video processing blocks.

9 masters access the video memory having burst size 32. The arbitration is set at 32 for each master.

The video processing blocks run at 100 MHz while the DDR2 runs at 150 Mhz, 64-bit.So I have to use clock-crossing bridges to connect to the memory. Are these bridges causing the bottleneck or is it something else ?

I am stuck at this for quite sometime now, I am simply not able to tune the pipeline for the required performance.

Would really appreciate any light on the issue.

Thanks

Foram

Hi,

Sorry I am stuck too, and I am not available now to give relevant advice. Maybe Jake or someone will help.

It is said that one may lose 5 to 7 clocks when using clock-crossing bridges. If you have time, you make check it by using the Signal Tap.

Bests,

avtx30

Foram,

Which video processing blocks are you using? If you are using Altera's Deinterlacer or Frame buffer then you can force them to use a different clock domain for the memory masters than for the video processing. This would allow you to connect the memory interfaces directly to the DDR2 memory controller without using the clock crossing bridges.

If you want to do this, edit the following files:

C:\altera\80\ip\deinterlacer\lib\vip_dil_hwfast.hpp

Change line 10 from

# define DIL_MEM_MASTERS_USE_SEPARATE_CLOCK false

to

# define DIL_MEM_MASTERS_USE_SEPARATE_CLOCK true

C:\altera\80\ip\frame_buffer\lib\vip_vfb_hwfast.hpp

Change line 13 from

# define VFB_MEM_MASTERS_USE_SEPARATE_CLOCK false

to

# define VFB_MEM_MASTERS_USE_SEPARATE_CLOCK true

Then when you reopen SoPC builder you will see that the memory masters have their own clock domain and you will have to connect things accordingly.

Jake

Hi Jake,

Thanks for the info :). Yes I am using Altera's Deinterlacer and Framebuffer IPs.

Hope this would simplify things a bit. I will try this today and update the result.

Thanks

Foram

In these multi-master configuration, Monitoring Wait request by all masters is one way to implement scheduling. The Avalon Master arbitration logic takes of the rest when ever a master tries to read/write into the SDRAM controller. Every Master has to monitor the Waitrequest before performing a write/read to the SDRAM controller.

--Sheshi

Hi,

I tried the separate clock domain for deinterlacer and framebuffer however somehow couldn't get it to work.

However I needed to get it work ASAP :(... so i modified the design and got rid of the extra master; for now i get live almost live frame rate. A couple of frames are still being dropped but the frame rate is acceptable.

once this deadline is over, i hope to investigate these suggestions and try and implement it. I wonder how these this board and the IPs are being used to process HD resolutions. Is it merely an arbitration issue ?

Thanks

Foram