SDRAM controller: Altera High Performance vs. Microtronix Multi-Port

Foram,

Which video processing blocks are you using? If you are using Altera's Deinterlacer or Frame buffer then you can force them to use a different clock domain for the memory masters than for the video processing. This would allow you to connect the memory interfaces directly to the DDR2 memory controller without using the clock crossing bridges.

If you want to do this, edit the following files:

C:\altera\80\ip\deinterlacer\lib\vip_dil_hwfast.hpp

Change line 10 from

# define DIL_MEM_MASTERS_USE_SEPARATE_CLOCK false

to

# define DIL_MEM_MASTERS_USE_SEPARATE_CLOCK true

C:\altera\80\ip\frame_buffer\lib\vip_vfb_hwfast.hpp

Change line 13 from

# define VFB_MEM_MASTERS_USE_SEPARATE_CLOCK false

to

# define VFB_MEM_MASTERS_USE_SEPARATE_CLOCK true

Then when you reopen SoPC builder you will see that the memory masters have their own clock domain and you will have to connect things accordingly.

Jake