Forum Discussion
Altera_Forum
Honored Contributor
17 years agoHi,
I am also using the 3c120 board for a video processing application and I am facing the same bandwidth issues. I have split the DDR2 in two separate 32-bit memories. Nios has full access to one while the other is shared by the video processing blocks. 9 masters access the video memory having burst size 32. The arbitration is set at 32 for each master. The video processing blocks run at 100 MHz while the DDR2 runs at 150 Mhz, 64-bit.So I have to use clock-crossing bridges to connect to the memory. Are these bridges causing the bottleneck or is it something else ? I am stuck at this for quite sometime now, I am simply not able to tune the pipeline for the required performance. Would really appreciate any light on the issue. Thanks Foram