RX_lock Intermittent after reset when PLL is outputting clock on LVDS Stratix IV

Question

I have a design that is using 2 LVDS Receiver Cores per FPGA.   The CCA has 2 Stratix IV FPGAs that are basically identical.  I have an external reset that goes to the Stratix IV FPGAs and one of the 4 LVDS Receivers intermittently fails to display an Rx_Lock (~1 out of 10 times).  Also once this happens no matter how many times I reset I can't get it to re-lock.  Re-powering the CCA or Re programming the FPGA solves the issue though.  I have followed the LVDS handbook for the reset circuit and I have double checked power to the FPGA and do not see any glitches.  If I swap the pins into the other core it follows the pins to that core.  Any ideas?

ash_r_intel · Answer

Hi Jonathan,Refer section 1.5.3 of the following guide:https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altlvds.pdfSuggest to check following points:1) Reset assertion duration of at least 10 ns.2) Ensure the input clock stability and jitter specifications.Regards.

jonathandt · Answer

Ash,

I have 2 instances of this in the Stratix IV FPGAs.  I am following the reset as described in Section 1.5.3.  I have checked the clock for excessive Jitter and have not noticed anything out of spec.  The one interesting item is that I have to reset both devices (the TX and the LVDS RX) for this to occur intermittently, but once it occurs there is no getting the FPGA Rx_Lock to become present almost like the PLL goes into an unknown state and will never re-lock until re-programmed or re-powered.  I can reset the RX or the TX individually and this never happens.   Is there anything that would induce the PLL to never re-lock again?

Jonathan

ash_r_intel · Answer

Hi Jonathan,Can you send the IP wizard generated top .vhd or .v file? We'll understand the settings that you have selected while generating the IP.Regards.

ash_r_intel · Answer

Hi Jonathan,Can you send the IP wizard generated top .vhd or .v file? We'll understand the settings that you have selected while generating the IP.Regards.

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RX_lock Intermittent after reset when PLL is outputting clock on LVDS Stratix IV

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