New Contributor
Regular ContributorHi Jonathan,
Refer section 1.5.3 of the following guide:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altlvds.pdf
Suggest to check following points:
1) Reset assertion duration of at least 10 ns.
2) Ensure the input clock stability and jitter specifications.
Regards.
New ContributorAsh,
I have 2 instances of this in the Stratix IV FPGAs. I am following the reset as described in Section 1.5.3. I have checked the clock for excessive Jitter and have not noticed anything out of spec. The one interesting item is that I have to reset both devices (the TX and the LVDS RX) for this to occur intermittently, but once it occurs there is no getting the FPGA Rx_Lock to become present almost like the PLL goes into an unknown state and will never re-lock until re-programmed or re-powered. I can reset the RX or the TX individually and this never happens. Is there anything that would induce the PLL to never re-lock again?
Jonathan
