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STATEABC's avatar
STATEABC
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2 months ago

Regarding the TX settings of MIPI CSI2 IP

In my Qsys project, I want to implement a function where the Test Pattern Generator IP sends the pattern to the MIPI CSI2 TX via an AXI stream. The MIPI CSI2 TX then sends the pixel data to link1 of ...
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STATEABC's avatar
STATEABC
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1 month ago

Hello,

Thank you very much for your suggestion.

I generated a project based on https://github.com/altera-fpga/agilex-ed-camera-ai?tab=readme-ov-file and compared it. Unfortunately, I found that the project you provided only has examples for MIPI RX and DPHY RX, and not the MIPI CSIX TX related parts. However, I can confirm that my MIPI RX part can work because my other project can output images via CAMERA->MIPI DPHY-MIPI CSI2 RX->HDMI.

Furthermore, I checked AXI-Stream, and the AXI input width and CSI-2 TX configuration data width are both 24 bits, with data type RGB888. (The previous CSI2 configuration screenshot shows that Pixels in parallel was changed from 4 to 1.)

Below is my mipi.qsys

The MIPI DPHY settings are shown in the image.

Are there any other relevant suggestions or reference examples? Any help is appreciated.