New Contributor
New ContributorHi ,
After modification, CSI2 TX's axi stream tready signal ability is high, TPG->CSI2 TX's number is normal.
However, this is also a new problem that has appeared, CSI2 T2X IP good image has been lost, but the reason is that the reason is that the signal tap is taken and the waveform is shown.
Is there any other construction?
Thx.
Regular ContributorHi,
From your description and the SignalTap capture:
Below are checks that typically isolate CSI-2 TX “no output” behaviors after AXI-side changes.
There is few things I suggest to check
Regards,
Wincent_Altera
New ContributorHello,
Thank you very much for your suggestion.
I generated a project based on https://github.com/altera-fpga/agilex-ed-camera-ai?tab=readme-ov-file and compared it. Unfortunately, I found that the project you provided only has examples for MIPI RX and DPHY RX, and not the MIPI CSIX TX related parts. However, I can confirm that my MIPI RX part works because my other project can output images via CAMERA->MIPI DPHY->MIPI CSI2 RX->HDMI.
Furthermore, I checked AXI-Stream, and the AXI input width and CSI-2 TX configuration data width are both 24 bits, with the data type being RGB888. (The previous CSI2 configuration screenshot showed that Pixels in parallel was changed from 4 to 1.)
Below is my mipi.qsys
The MIPI DPHY settings are shown in the image.
Are there any other relevant suggestions or reference examples?
Any help is appreciated.
Regular ContributorHi STATEABC ,
Initially the MIPI CSI2 TX axi stream ready signal remains low, and it doesn't process axi stream data from the TPG. After modification, CSI2 TX's axi stream tready signal ability is high, TPG->CSI2 TX's number is normal.
>> Do you mind to share with me what change had been make to enable back the TX AXI signal ?
>> Just wondering what could potential make the image lost
However, this is also a new problem that has appeared, CSI2 T2X IP good image has been lost, but the reason is that the reason is that the signal tap is taken and the waveform is shown.
>> Do you means in previously before modifying , when the MIPI CSI2 TX axi stream ready signal remains low, the image look good ?
Sorry I am bit confuse , just trying to understand better the problem so that I can provide an accurate answer to your queries. Looking forward to hear back from you soon.
Regards
Wincent
New ContributorHello,
I'm very happy to receive your reply.
In my project, I initially connected via TPG->CSI2 TX, but the axi stream ready was always low.
The TPG configuration is shown in the image.
Later, I realized that a direct connection might not be possible.
So, I referred to another project I worked on and added other IPs after the TPG. Now my data stream is: TPG IP->Bits Per Color Sample Adaper IP->Pixels in Parallel Converter IP->CSI2 TX. The two IPs in the middle convert the 10 bits per color sample/4 pixels in parallel TPG to 8 bits per color sample/1 pixel in parallel pixel data and pass it to CSI2 TX. Then, the CSI2 TX axi stream tready signal can be pulled high.
This is a very strange phenomenon. I don't think there's any difference between the converted TPG and a direct connection with 8 bits per color sample/1 pixel in parallel TPG, but it does make the tready signal go high. It would be great if you could explain why.
Now, to answer your other question, I believe the TPG image has always been normal because both the converted TGP axi stream and the 8 bits per color sample/1 pixel in parallel TPG output the image directly to HDMI.
Furthermore, I read the CSI2 TX registers. Even though I wrote 1920 and 1080 to 0x160 VIDEO_INTF0_WIDTH and 0x170 VIDEO_INTF0_HEIGHT_F0 respectively, 0x150 VC0_MODE_MATCH remained at 0. Does this mean the input data resolution and the video stream's width and height are mismatched, resulting in no CSI2 TX output?
These phenomena are very confusing to me, and I don't know where the problem lies. Thank you very much for your reply. Looking forward to hearing back from you soon.
New ContributorHello,
Thank you very much for your suggestion.
I generated a project based on https://github.com/altera-fpga/agilex-ed-camera-ai?tab=readme-ov-file and compared it. Unfortunately, I found that the project you provided only has examples for MIPI RX and DPHY RX, and not the MIPI CSIX TX related parts. However, I can confirm that my MIPI RX part works because my other project can output images via CAMERA->MIPI DPHY->MIPI CSI2 RX->HDMI.
Furthermore, I checked AXI-Stream, and the AXI input width and CSI-2 TX configuration data width are both 24 bits, with the data type being RGB888. (The previous CSI2 configuration screenshot showed that Pixels in parallel was changed from 4 to 1.)
Below is my mipi.qsys
The MIPI DPHY settings are shown in the image.
Are there any other relevant suggestions or reference examples?
Any help is appreciated.
New ContributorHello,
Thank you very much for your suggestion.
I generated a project based on https://github.com/altera-fpga/agilex-ed-camera-ai?tab=readme-ov-file and compared it. Unfortunately, I found that the project you provided only has examples for MIPI RX and DPHY RX, and not the MIPI CSIX TX related parts. However, I can confirm that my MIPI RX part can work because my other project can output images via CAMERA->MIPI DPHY-MIPI CSI2 RX->HDMI.
Furthermore, I checked AXI-Stream, and the AXI input width and CSI-2 TX configuration data width are both 24 bits, with data type RGB888. (The previous CSI2 configuration screenshot shows that Pixels in parallel was changed from 4 to 1.)
Below is my mipi.qsys
The MIPI DPHY settings are shown in the image.
Are there any other relevant suggestions or reference examples? Any help is appreciated.
