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Altera_Forum
Honored Contributor
Honored Contributorread problem with DDR2 HP II controller
Hello
I am simulating DDR2 Hi performance controller that came with Q9.1. The problem is my simulation works fine for MAXIMUM_ROWS = 16'h0018 MAXIMUM_COLS = 10'h3F8 but read back fails with MAXIMUM_ROWS = 16'h0019 MAXIMUM_COLS = 10'h3F8 (I assert the read_req but never receive a read_valid back from the controller) Somewhere there are write requests in the system that are left unfinished while my state machine switches to reads. I am attaching my state machine + a snapshot of waveform. The snap shows end of writes and beginning of read for which the read_valid never comes if MAX_ROWS are greater than 0x18. Can someone guide me to whats wrong; all my debugging skills have failed so far. Thanks a million and Regards.5 Replies
Altera_Forumcheck that you are writing out both beats on the local side if you are using half rate controller. the controller will hang if the write is completed.
- Altera_Forum
Hello
Do you mean the local_write_req should be asserted through out the write burst? I think I am already doing that. Can you elaborate a bit more please? - Altera_Forum
What are your interface specs? Half rate DDR3? If you have a half rate controller you need 2 beats of write data on the local side, ie a 2 write burst, over 2 clock cycles, burst begin only goes high for the first one however. This is assuming local size is set to 2. If you only have half this data then you need to set local size to 1 for that write.
- Altera_Forum
Hello
Yes, I am using half rate DDR2 and local size = 2 and i am doing 2 beats, burst begin is high for 1 cycle and low for 1. I attached my state machine and a waveform capture of these signals in my previous post, if you want to take a look. Thank you! Regards - Altera_Forum
you say the read goes out but data never comes back?, are you sure the read went out (externally). i would probe many more signals in your simulation to get a better picture of what is happening.
