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Altera_Forum
Honored Contributor
Honored Contributorread problem with DDR2 HP II controller
Hello I am simulating DDR2 Hi performance controller that came with Q9.1. The problem is my simulation works fine for MAXIMUM_ROWS = 16'h0018 MAXIMUM_COLS = 10'h3F8 but read back fa...
Altera_ForumHonored Contributor
Honored ContributorWhat are your interface specs? Half rate DDR3? If you have a half rate controller you need 2 beats of write data on the local side, ie a 2 write burst, over 2 clock cycles, burst begin only goes high for the first one however. This is assuming local size is set to 2. If you only have half this data then you need to set local size to 1 for that write.
