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Altera_Forum
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15 years ago

read problem with DDR2 HP II controller

Hello I am simulating DDR2 Hi performance controller that came with Q9.1. The problem is my simulation works fine for MAXIMUM_ROWS = 16'h0018 MAXIMUM_COLS = 10'h3F8 but read back fa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hello

Do you mean the local_write_req should be asserted through out the write burst? I think I am already doing that.

Can you elaborate a bit more please?