R-TILE PIPE DIRECT MODE SIMULATION PHY STATUS ISSUE IN RESET RELEASE SEQUENCE

Hi pradeep_12 ,

The guide shows txdetectrx_i being asserted while the lane is in P1 and the transmitter is electrically idle; it must not simply be held at an arbitrary level after PCS reset. Your waveform appears to leave the lane in P1 and does not show the complete detect-command/deassertion sequence.

Main issues visible in your waveform

• powerdown_i appears to remain at 2'b10/P1. You must transition it to P0 after receiver detection.
• txelecidle_i is not shown. Drive it to 4'hF during P1 receiver detection.
• Do not assert rxstandby_i during bring-up; that requests RX standby and prevents normal receiver activity. The PHY reports standby through rxstandbystatus_o.
• txdetectrx_i should be treated as a receiver-detect command and then returned inactive after the phystatus/rxstatus response.
• Use a sticky debug latch for phystatus, because a one-cycle pulse can easily be missed in a wide Questasim waveform view
• After the receiver-detect pulse, you will only see cdrlockstatus_o, cdrlock2data_o, RX clock, and reset_status_n_o become active if the simulation includes a valid serial link partner or loopback data. 

Regards,
Wincent_Altera