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foft's avatar
foft
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Quartus ram block sharing bug on Cyclone V

I am using a Cyclone V 5CEBA2F23C8 in my design for an Atari XL recreation - the EclaireXL.

The Cyclone V has been excellent and I am very impressed with the technology. The fractional PLLs are really great, you should include them in the smaller FPGA families too! If there was a 5V tolerant version that would be even better.

Anyway to the point. I have now filled up the block memory and after some recent changes, when I compile my design I see that a block is inferred for the 6502 CPU and ALSO used explicitly for the zpu memory. Using the block twice is clearly a great efficiency if it can be done and still work. However the issue I have with this is: the block gives incorrect data where it is inferred for the CPU!

I was hoping this would be solved in the next Quartus versions but after a few iterations it has not been addressed. I'm not on Quartus Lite 20.1.1. So I thought it may be something that Intel is not aware of.

In order to workaround this bug, is there a way to tell Quartus not to use memory blocks twice when synthesizing the design?

12 Replies

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Hi Mark,


    Is it possible to attach the qar design here. Ill try to replicate and see what can I find at my end.


    Thanks,

    Regards


      • foft's avatar
        foft
        Icon for Occasional Contributor rankOccasional Contributor
        5 years ago

        Hi Syafieq,

        Just wanted to check that I created/attached the .qar file ok and you were able to pick it up?

        Thanks,

        Mark

    • foft's avatar
      foft
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      To restate the issue more simply to increase changes of a reply.

      I have a design that used to work well for the Cyclone V 5CEBA2F23C8. As the FPGA filled up Quartus decided to share the same block ram between parts of the design.

      For some reason, a bug in the design, or a bug in Quartus, the sharing of block ram does not work correctly.

      Is there a way to disable sharing block ram between multiple parts of the design?

      • sstrell's avatar
        sstrell
        Icon for Super Contributor rankSuper Contributor
        5 years ago

        Without seeing the design, it's hard to understand what you mean. Are you saying that you've inferred or instantiated a RAM and the same physical RAM block is being shared using multiple ports? Can you show some code or what you're seeing in the RTL viewer or the Technology Map Viewer?

        There are packing and merging options you could check in Assignments menu -> Settings -> Compiler Settings -> Advanced Analysis & Synthesis Settings, but they're mostly for registers.

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Hi Mark,


    Yes, you can repost it with qar file attached.


    Thanks,

    Regards